The present invention concerns an erasing circuit for an electrically erasable and programmable semiconductor memory (hereinafter referred to as "EEPROM") and a method thereof, particularly an automatic erasing optimization circuit for sensing and optimizing the erasing state of the memory cell in a selected page of a flash-type EEPROM, and a method thereof.
Generally, the first non-volatile memory device for storing data is an EPROM in which the data is electrically programmed and erased by ultraviolet light. Hence, whenever the program presently stored in the EPROM is changed with another, the memory device must be removed from the system containing it and exposed to ultraviolet light to erase the presently stored program, so that this procedure may take much time.
Moreover, although there has been developed an electrically erasable and programmable read only memory (EEPROM), each of the memory cells of the EEPROM requires two transistors, one of which is a selection transistor to select a memory cell according to an address, and the other which is to read out the data stored in the selected memory cell, so that it is difficult to achieve a high integrated memory array with a large storage capacity.
In order to resolve the problems consisting in the production of a high integrated memory array with a large storage capacity, there was introduced a flash-type EEPROM that may be erased in a single operation, disclosed in the pages 616-619, International Electron Device Meeting published by IEEE, and in U.S. Pat. No. 4,698,787 issued in 1984. A single memory cell of the flash-type EEPROM includes a floating-gate field-effect transistor in which a floating-gate and a control gate are stacked with a thin tunnel oxide interposed between the floating gate and the channel. In such a memory cell, the programming is achieved by applying a high voltage of 12 V-15 V to the control gate and a high voltage of 6 V-7 V to the drain region so as to cause hot electrons generated in the channel region to tunnel into the floating-gate to form a high threshold voltage state of 6 V-10 V. On the other hand, the erasing is achieved by applying a high voltage of 12 V-14 V to the source region so as to cause electrons to pass from the floating-gate to the source region by Fowler-Nordheim tunneling effect to form a high threshold voltage of 0.1 V-1.2 V. In the erasing, as shown in FIG. 5b of the above U.S. Patent, the sources of the memory cells are connected with a common source line supplied with an erasing voltage of high level.
In this case, there is needed an additional source voltage supply for generating a high voltage in order to produce hot carriers in the channel for programming. Further, since erasing is performed through the source diffusion layer, if the source diffusion layer is separately divided, only the cell in a specified block may be erased, but in order to confirm whether the cell is properly erased or overerased, it is necessary to perform a special program for confirming the erasing when externally programming on the circuit board to the chip.
The other type of the flash-type EEPROM is disclosed in the pages 33-34 of Symposium of VLSI Technology, 1988. This EEPROM is a NAND type, wherein a single memory string includes eight cell transistors commonly occupying the bit lines and a ground line. Hence, this is advantageous for integration, and a single power source is used to program, erase and read out the memory with low power consumption because of tunneling effect, namely, Fowler-Nordheim tunneling effect by a high voltage through the thin dielectric layer (or tunnel oxide) between the drain and floating-gate. However, when a high voltage of about 13 V is applied to word lines in order to erase the memory, if one of the memory cells in the memory string is exceedingly erased thus having a high threshold voltage, the current flowing in the memory cell having the high threshold voltage prevents the current flowing in the memory string when reading out another cell in the memory string. This results from the fact that the cell transistors in the NAND-type EEPROM are connected in series. Consequently, when reading out another cell in the string, the cell having the high threshold voltage due to the excessive erasing causes the speed of the reading out to be slowed down, or in the worst case even to misapprehend all the cells in the string for being erased.